Plasma etching and reactive ion etching (RIE) are important tools in semiconductor fabrication. These etches, which utilize excited ions as etchants, offer a high degree of anisotropy compared to wet etchants. Because of this, they are widely used in many integrated chip fabrication processes. For example, in the back end of the line processing, RIE etching is often used to provide a large sidewall angle for metal and via levels.
The ions which are used in these plasma based etches can induce a charge on exposed conductive levels (e.g., polysilicon gates, aluminum metal levels). During the course of the etching process, this induced charge can build up leading to processing and reliability problems. For example, the buildup of charge on a polysilicon gate can cause charge dissipation through the underlying gate oxide, which, depending on the amount of charge buildup and the oxide thickness, may lead to either device degradation or complete gate dielectric breakdown and device failure.
It is common in the semiconductor fabrication industry to include protection circuitry associated with devices. The protection circuitry allows plasma charge buildup to be dissipated from a conductive layer before it causes damage. For example, capacitors are often attached to a polysilicon layer and used for the purpose of dissipating built up charge. Unfortunately, the use of these devices requires relatively large silicon area. Alternative methods of charge dissipation may require metal wiring to connect conductive layers to discharge junctions. The metal wiring utilized in these methods is increasingly difficult to design as scaling often fails to allow a geometric shrink of metal levels. As technologies continue to shrink and silicon area becomes more valuable it is increasingly important to find alternative methods of charge dissipation which are unrestrictive to the functional circuitry.